Welcome to the Verilog Guide

This section covers the following topics

Introduction To Verilog

Learn the Basics of Verilog HDL and implement various circuits using Verilog.

Finite State Machines

Design a Verilog-based FSM that enhances your circuits with efficient sequential control and decision-making capabilities.

🖥️

MIPS Single Cycle Processor

Build an exciting MIPS single cycle processor which will allow you to run MIPS hardware commands.

💾

Registers

Learn about the registers in MIPS ISA.

📖 Introduction to Verilog

THEORY :

Open

Documentation Link

Video Explanation of Theory:

Theory Vid Part 1 (INTRO TO VERILOG-LOGIC GATES-ADDERS-SUBTRACTORS)

Theory Vid Part 2 (PARITY-TILL END)

IMPLEMENTATION:

How to Run Verilog Files in Quartus?

Sample Codes: Link

Video Explanation of Select Codes:

Topic	Video Link
Verilog Syntax	Verilog Syntax
Adder Subtractor	Adder Subtractor
DEMUX	DEMUX
Counter	Counter
Decoder	Decoder

🚦 Finite State Machines

THEORY :

Open

Documentation Link

Video Explanation of Concept:

IMPLEMENTATION:

Code Bank: Link to Sample Codes

Video Explanation of Code (From Documentation):

Examples of FSM along with Code explanation

🖥️ Single Cycle MIPS Processor

THEORY :

Open

Documentation Link

Video Explanation of Concept:

IMPLEMENTATION:

Main Code

Video Explanation of Code :

Topic	Video Link
Code Modules 1 to 5 explained	Video Link
Code Modules 6 to 10 explained	Video Link
All Testbenches explained	Video Link

Code Bank : Link to Code Bank

Link to Sample Codes

Modification Questions & Solution	Video Explanation
Modify given code to include the Andi, Ori and Xori instructions	N/A
Modify given code to include the Jr (Jump Register) instruction	Video Explanation

Assignment 3

💾 Registers

THEORY :

Open

Documentation Link

Link to Sample Codes

Welcome to the Verilog Guide

Introduction To Verilog

Finite State Machines

MIPS Single Cycle Processor

Registers

📖 Introduction to Verilog ​

🚦 Finite State Machines ​

🖥️ Single Cycle MIPS Processor ​

💾 Registers ​

📖 Introduction to Verilog

🚦 Finite State Machines

🖥️ Single Cycle MIPS Processor

💾 Registers