Welcome to the Verilog Guide
This course covers the following topics-
Introduction To Verilog- Learn the Basics of Verilog HDL.Finite State Machines- Design a Verilog-based Finite State Machine (FSM) that enhances your circuits with efficient sequential control and decision-making capabilities.MIPS Single Cycle Processor- Build an exciting MIPS single cycle processor which will allow you to run MIPS hardware commands.
Introduction to Verilog
Theory :
Documentation: Link to Main Documentation :simple-googledrive:
Video Explanation of Theory:
1. Theory Vid Part 1 (INTRO TO VERILOG-LOGIC GATES-ADDERS-SUBTRACTORS) :simple-youtube:
2. Theory Vid Part 2 (PARITY-TILL END) :simple-youtube:
Implementation :
How to Run Verilog Files in Quartus: How to Run ? :simple-youtube:
Sample Codes: Link to Sample Codes :simple-github:
Video Explanation of Select Codes:
1. Verilog Syntax :simple-youtube:
2. Adder Subtractor :simple-youtube:
3. DEMUX :simple-youtube:
4. Counter :simple-youtube:
5. Decoder :simple-youtube:
Assignment 1: Download Here
Finite State Machines
Theory :
Documentation: Link to Main Documentation :simple-googledrive:
Video Explanation of Concept:
1. Main Concept :simple-youtube:
2. Syntax (Optional) :simple-youtube:
Implementation :
Video Explanation of Code (From Documentation):
Examples of FSM along with Code explanation :simple-youtube:
Code Bank:
Link to Sample Codes :simple-github:
Assignment 2: Download Here
Single Cycle MIPS Processor
Theory :
Documentation: Link to Main Documentation :simple-googledrive:
Video Explanation of Concept:
1. Control Unit Theory :simple-youtube:
2. Datapath Theory :simple-youtube:
Implementation :
Video Explanation of Code (From Documentation) :
1. Code Modules 1 to 5 explained :simple-youtube:
2. Code Modules 6 to 10 explained :simple-youtube:
3. All Testbenches explained :simple-youtube:
Code Bank:
Link to Sample Codes :simple-github:
Assignment 3: Download Here